The trend in semiconductor fabrication is to increase circuit integration by shrinking device sizes on a chip. Many new techniques have been developed to accomplish this. For example, the Deep Ultra-Violate (DUV) technique is commonly used to enhance the resolution of photolithography in semiconductor fabrication by using a light source having wavelength of 193 nm or 157 nm. The development of DUV technology has advanced semiconductor manufacturing technology into deep sub-micron processes. As to circuit integration, the self-alignment technique has increased the level of integration of circuits.
The size of non-volatile memory cells (memory cells which store data without power) have been decreasing by applying new fabrication processes or new structures. A variety of memory devices have been proposed or used in non-volatile memories. One commonly known device is the Flash EPROM (Erasable and Programmable Read-Only Memory). A flash EPROM typically comprises a large matrix of memory cells formed on a substrate, wherein each cell is formed by a floating gate transistor. The floating gate transistor of the flash memory cell typically comprises a floating gate disposed between a control gate and a channel region of the substrate. The floating gate is electrically isolated from the control gate and the channel region by thin insulating films or layers. The flash memory cell is operated by removing (erasing) electrons from the floating gate or placing (program) electrons on the floating gate. This process is achieved by applying a voltage between the control gate and the source or drain and is called Fowler-Nordheim Tunneling.
The floating gate of the flash memory cell may be formed by an electroconductive (e.g. polysilicon) gate layer covered by an oxide mask which provides isolation between the floating gate and the word line. Conventional oxidation methods are typically used to form the floating gate oxide masks during the fabrication of the memory cell matrix on the substrate. FIG. 1 shows a substrate 100 having two different areas 110 and 120 on which conventional first and second floating gate structures 111 and 121 are formed. The first floating gate structure 111 formed on the first area 110 of the substrate 100 comprises a first tunnel oxide 112 disposed on the substrate 100, a first floating gate 113 disposed on the first tunnel oxide 112 and a first oxide mask 114 disposed on the first floating gate 113. The second floating gate structure 121 formed on area 120 of the substrate 100 comprises a second tunnel oxide 122 disposed on the substrate 100, a second floating gate 123 disposed on the second tunnel oxide 122, and a second oxide mask 124 disposed on the second floating gate 123. The first and second oxide masks 114 and 124 have been formed by a conventional oxidation method and have substantially the same thickness.
New fabrication processes have been developed to achieve continued flash memory size reductions. One such process is the chemical-mechanical polish (CMP) floating gate formation process. FIG. 2 shows a substrate 200 having two different areas 210 and 220 on which first and second floating gate structures 211 and 221 are formed by an existing CMP floating gate process. The first floating gate structure 211 formed on the first area 210 of the substrate 200 comprises a first tunnel oxide 212 disposed on the substrate 200, a first floating gate 213 disposed on the first tunnel oxide 212, and a first oxide mask 214 disposed on the first floating gate 213. The second floating gate structure 221 formed on area 220 of the substrate 200 comprises a second tunnel oxide 222 disposed on the substrate 200, a second floating gate 223 disposed on the second tunnel oxide 222, and a second oxide mask 224 disposed on the second floating gate 223.
Although the CMP process improves the kissing effect (i.e., where an oxide mask produced by an oxidation method extends across the narrow space between two floating gates and bridges them together) and produces a square top oxide mask profile that lowers the probability of cell to cell bridging and allows for downward scaling, the oxide masks 214 and 224 are not of substantially the same thickness, as depicted in FIG. 2. The non-uniform oxide mask thicknesses undesirably widen the forward tunneling voltage (FTV) range of the EPROM. In addition, as depicted in FIG. 2, the relatively thick oxide mask material (encircled) above the tip regions 213.1, 223.1 of the floating gates 213, 223, increases the FTV of the gates, thus, slowing the erase performances of the cells.
Accordingly, there is a need for floating gate structures with reduced and more uniform forward tunneling voltages.